1. Field of the Invention
The present invention relates to a data output buffer for semiconductor devices, and more particularly, to a data output buffer having a present structure.
2. Background of the Related Art
FIG. 1 is a block diagram for generating a control signal for use in semiconductor devices.
An address transition detecting unit 10 senses when an inputted address is shifted to generate an address transition detection signal atd. An equalization signal generating circuit 20 generates an equalization signal peq according to the address transition detection signal atd. A control and delay circuit 30 generates various control signals and delay signals (peqdly, poe . . . ) according to the inputted equalization signal peq.
FIG. 2 is a detailed circuit diagram of a conventional data output buffer. The operation of the data output buffer will be described by reference to FIG. 3. In FIG. 3, an address Add, a chip select signal/CS, an output enable signal/OE and a write enable signal/WE are signals used for the operation of the common semiconductor memory devices.
FIG. 2 has a structure in which in a given period of time after transition of an address is detected in a read operation and a read cycle then begins, a data sodin from a sense amplifier (not shown) reaches a data output buffer and at once a pulse output enable signal poe operates the data output buffer, which then outputs a data. This will be described in detail below.
If the read operation begins, the output signal sodin of the sense amplifier reaches the data output buffer. As the pulse output enable signal poe through inverters I1 and I2 is at a LOW level, that is, the outputs of NAND gates ND1 and ND2 are at HIGH levels in a standby mode, PMOS and NMOS transistors P1 and N1 are turned off. Thus, the output dout is changed to a HIGH impedance level by an external termination circuit 40. Thereafter, if the pulse output enable signal poe becomes HIGH, the output sodin of the sense amplifier is transferred to the output dout. If the output sodin of the sense amplifier is HIGH, the output of the NAND gate ND1 becomes LOW. The signal of the LOW level is applied to the gate terminal of the PMOS transistor P1 via the inverters I3 and I4. Accordingly, the PMOS transistor P1 is turned on, so that the output dout becomes HIGH.
On the contrary, the output of the NAND gate ND2 becomes HIGH. The signal of the HIGH level is inverted by the inverter 16 and is then applied to the gate terminal of the NMOS transistor N1. Therefore, the NMOS transistor N1 is turned off.
This type of the data output buffer has an external load and a rapid read cycle. Furthermore, if this data output buffer has to output data opposite to data of the previous cycle, the output dout must largely swing from 0V to Vcc. Therefore, there is a possibility that noise may occur due to delayed speed and increased peak current. In particular, if the data output buffer is constructed in a wide bit and has to output a plurality of data at the same time, the output dout is changed from a LOW level to a HIGH level or HIGH level to LOW level. Therefore, generation of noise due to increased peak current is inevitable.
Accordingly, the present invention is contrived to substantially obviate one or more problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a data output buffer having a preset structure in which the output of the data output buffer is preset to an intermediate level in advance and is then converted to an effective data level depending on an input data.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objectives and other advantages of the invention may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these objects and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, a data output buffer having a preset structure according to the present invention is characterized in that it comprises a plurality of groups, each group having two data output buffers, a preset driver for precharging or discharging any one output of two output buffers in each group, a control circuit for generating a control signal to drive the preset driver when outputs of the two output buffers in each group are same, and a set circuit connected between the outputs of the two data output buffers in each group, for making the outputs of the two data output buffer in each group the same level.
In another aspect of the present invention, it is to be understood that both the foregoing general description and the following detailed description of the present invention are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.